Power mosfet and method for forming same using a self-aligned body implant

ABSTRACT

A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

RELATED APPLICATION

[0001] This application is based upon prior filed copending provisionalapplication No. 60/219,858 filed Jul. 20, 2000, the entire disclosure ofwhich is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to the field of semiconductordevices, and, more particularly, to a trench-gated power MOSFET.

BACKGROUND OF THE INVENTION

[0003] The electronic industry has demonstrated a great need for smalldiscrete power MOSFETs with low on-resistances (RDSon), large blockingvoltages (VDSBR), and low gate charges in addition to adequateruggedness. Ruggedness defines the safe operating area (SOA) and theunclamped inductive switching (UIS) of the device. With an optimumcombination of these characteristics, extremely low on-state powerlosses and switching losses can be achieved, resulting in high powerconversion efficiencies in systems such as DC-DC converters.

[0004] Ultra dense trench-gated power MOSFET technology has beendeveloped to meet these needs. By shrinking cell pitch, i.e., reducingthe size of the power MOSFET so that more power MOSFETs can be formedper square area of silicon, a lower on-resistance can be achieved. Butoften this is accompanied by a decrease in device ruggedness. In orderto resolve this negative impact, the device having a reduced cell pitchmust be designed to absorb more energy (including DC and dynamic powerdissipations) before catastrophic failure occurs.

[0005] The basic concept of trench-gated power MOSFET technology isillustrated with reference to FIGS. 1-3. FIG. 1 represents aconventional trench-gated power MOSFET 10. A gate 12 is in a trench 14formed within a P-well 16. With respect to forming the source/bodycontact regions 18, a corresponding etch mask must be aligned to thetrench 14. The dielectric layer 20 between the source electrode 22 andthe gate oxide layer 24 overlays a portion of the flat surface of the N+source region 26. The dimension of the dielectric layer 20 that overlaysthe N+ source region 26 is determined by the maximum gate-source rating.Therefore, the minimum cell pitch of the conventional structure islimited by the source/body contact masking misalignment tolerance plusthe spacing taken by the surface dielectric layer 20.

[0006] This limitation is eliminated by using the trench technologyillustrated in FIGS. 2 and 3. In the resulting device structure 28, thegate 12 is recessed into the trench 14, leaving a recess region largeenough for the dielectric layer 20. The depth of the recess region,which will determine the final thickness of the dielectric layer 20, isdetermined by the maximum gate-source rating. After the dielectric layer20 has been deposited, it is etched back using the flat silicon surface32 as the ending point.

[0007] Compared to the conventional trench-gated power MOSFET 10 asshown in FIG. 1, this device 28 provides very high channel densities.The cross sectional views of this device 28 at the different locationslabeled 3 a and 3 b in FIG. 2 are respectively illustrated in FIGS. 3aand 3 b. In order to form the device 28 with a very small cell pitchwithout the stringent requirement of the source/body contact etch maskstep, the P+ source/body contact region 18 is interrupted andperiodically placed along its N+ stripe, where the N+ source region 26is completely excluded.

[0008] Unfortunately, the periodic placement of the P+ source/bodycontact region 18 increases the on-resistance of the device 28, as wellas the base resistance and the common base current gain of the parasiticBJT. The parasitic BJT is formed by the N+ source region 26, the P-well16 and the N epitaxial layer 9. As a consequence, the parasitic BJT willbe turned on at a very low current, resulting in a poor SOA and a lowerUIS capability.

SUMMARY OF THE INVENTION

[0009] In view of the foregoing background, it is therefore an object ofthe present invention to provide a trench-gated power MOSFET with areduced on-resistance and an associated method for forming the same.

[0010] It is another object of the present invention to provide thetrench-gated power MOSFET without decreasing device ruggedness.

[0011] These and other advantages, features and objects in accordancewith the present invention are provided by a method for making a powerMOSFET comprising forming a trench in a semiconductor layer, forming agate dielectric layer lining the trench, forming a gate conducting layerin a lower portion of the trench, and forming a dielectric layer to fillan upper portion of the trench.

[0012] The method preferably further includes removing portions of thesemiconductor layer laterally adjacent the dielectric layer so that anupper portion thereof extends outwardly from the semiconductor layer.Spacers are preferably formed laterally adjacent the outwardly extendingupper portion of the dielectric layer, and are preferably used as aself-aligned mask for defining source/body contact regions.

[0013] The resulting trench-gated power MOSFET is advantageously formedwith a reduced on-resistance without degrading device ruggedness. Theon-resistance is reduced since each MOSFET includes a source/bodycontact region. The source/body contact region provides an efficientshort between the source and body regions of the MOSFET. As a result,device ruggedness is increased.

[0014] In addition, the on-resistance is reduced because the cell pitchof the power MOSFET is reduced as a result of the dielectric layer beingformed completely within the trench. In other words, the dielectriclayer is not on the surface of the source regions which would minimizethe contact region between the source regions and the source electrode.

[0015] Another factor for reducing the on-resistance and the cell pitchof the power MOSFET is a result of using the spacers as a self-alignedmask for implanting dopants into the body region for defining thesource/body contact regions. Since the spacers are self-aligned with theoutwardly extending dielectric layer, source/body contact maskingmisalignment tolerances are avoided.

[0016] Another embodiment of the present invention is to further use thespacers as a self-aligned mask for removing a portion of thesemiconductor layer not covered by the spacers prior to defining thesource/body contact regions. With a portion of the semiconductor layerremoved, lower energy is needed to implant the dopants for forming thesource/body contact regions.

[0017] In addition, the source/body contact regions can preferably beformed deeper within the semiconductor layer as a result of a portionthereof being removed. This decreases the base resistance and the commonbase current gain of the parasitic BJT, which improves deviceruggedness, i.e., the safe operating range (SOA) and the unclampedinductive switching (UIS) of the power MOSFET are increased.

[0018] Removing portions of the semiconductor layer is performed to adepth equal to or less than about 1 micron. The gate conducting layer isrecessed in the trench within a range of about 0.2 to 0.8 microns froman opening thereof. The power MOSFET may be formed to have a cell pitchof about 0.5 microns, for example. The trench-gated power MOSFET may beeither an n-channel or p-channel power MOSFET.

[0019] Another aspect of the present invention is directed to a MOSFETcomprising a semiconductor layer having a trench therein, a gatedielectric layer lining the trench, and a gate conducting layer in alower portion of the trench. The MOSFET preferably further includes adielectric layer in an upper portion of the trench and extendingoutwardly from the semiconductor layer. Source regions are preferablyadjacent the outwardly extending dielectric layer, and source/bodycontact regions are preferably laterally spaced from the gate conductinglayer.

[0020] Another embodiment of the power MOSFET is with respect to thesource regions, wherein a portion of the source regions include a recessover the source/body contact regions. In yet another embodiment, thesource regions includes an opening exposing the body region so that thesource electrode is in contact with the source/body contact regions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a conventional trench-gated power MOSFET according tothe prior art.

[0022]FIG. 2 is a top planar view of a trench-gated power MOSFET formedusing trench technology according to the prior art.

[0023]FIGS. 3a and 3 b are cross-sectional views of the trench-gatedpower MOSFET illustrated in FIG. 2 respectively taken along lines 3 aand 3 b.

[0024]FIG. 4 is a flow chart illustrating the method for making atrench-gated power MOSFET in accordance with the present invention.

[0025] FIGS. 5-13 are cross-sectional views of a portion of atrench-gated power MOSFET illustrating the process steps in accordancewith the preset invention.

[0026] FIGS. 14-15 are cross-sectional views of a portion of adjacenttrench-gated power MOSFETS illustrating the path of the avalanchebreakdown current based upon the depth of the source/body contactregions in accordance with the preset invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The present invention will now be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. Like numbers refer to like elements throughout. Thedimensions of layers and regions may be exaggerated in the figures forgreater clarity.

[0028] Referring now to FIG. 4, a method for making a trench-gated powerMOSFET in accordance with the present invention is described. From thestart (Block 40), a trench is formed in a semiconductor layer at Block42, and a gate dielectric layer is formed to line the trench at Block44. A gate conducting layer is then formed in a lower portion of thetrench at Block 46. A dielectric layer is formed to fill an upperportion of the trench at Block 48.

[0029] The method further includes removing portions of thesemiconductor layer laterally adjacent the dielectric layer so that anupper portion thereof extends outwardly from the semiconductor layer atBlock 50. Spacers are formed laterally adjacent the outwardly extendingupper portion of the dielectric layer at Block 52, and the spacers areused as a self-aligned mask for defining source/body contact regions atBlock 54.

[0030] The method according to the present invention advantageouslyprovides a high density power MOSFET with source/body contact regionsthat are formed in a self-aligned manner using the spacers. Since thespacers are self-aligned with the outwardly extending dielectric layer,the minimum cell pitch of the power MOSFET is not limited by source/bodycontact masking misalignment tolerances.

[0031] In addition, the on-resistance is decreased as a result of eachMOSFET having source/body contact region. This also helps to decreasethe base resistance and the common base current gain of the parasiticBJT. The parasitic BJT will be turned on at a higher current, resultingin an improved SOA and a higher UIS capability.

[0032] In addition, the on-resistance is reduced because the cell pitchof the power MOSFET is reduced as a result of the dielectric layer beingformed completely within the trench. In other words, the dielectriclayer is not on the surface of the source regions which would minimizethe contact region between the source regions and the source electrode.

[0033] The process steps for making a trench-gated power MOSFET inaccordance with the present invention will now be described withreference to FIGS. 5-13. Even though an n-channel power MOSFET 70 isillustrated in the referenced figures, the process steps may also beapplied for forming a p-channel power MOSFET, as readily appreciated byone skilled in the art.

[0034] An n-type epitaxial layer 9 is formed on a semiconductorsubstrate 8. The semiconductor substrate 8 is also of the n-type and ispreferably silicon. The epitaxial layer 9 supports the drain-to-sourcebreakdown voltage of the power MOSFET 70, as readily understood by oneskilled in the art.

[0035] A pad oxide layer 72 is grown on the epitaxial layer 9, followedby a p-type dopant implant to form the p-well or body region 16 of thepower MOSFET 70. The p-type dopant, such as Boron, is implanted using adose within a range of about 1E13/cm² to 5E14/cm², for example, and atan energy level within a range of about 40 to 200 keV, for example.

[0036] A mask 74 is formed on the surface of the pad oxide layer 72 fordefining the trench 14. The mask 74 may be a low temperature oxidelayer, for example. The body region 16 and the epitaxial layer 9 areetched to form the trench 14, as illustrated in FIG. 5. The mask 74 isthen removed.

[0037] A gate dielectric layer 24 is grown on the side walls and abottom wall of the trench 14, and on the surface of the body region 16.The gate dielectric layer 24 has a thickness within a range of about 10to 100 nm. Conducting material 25, such as polysilicon, is deposited inthe trench 14 and on the surface of the gate dielectric layer 24, asillustrated in FIG. 6.

[0038] Referring now to FIG. 7, the polysilicon 25 is removed from thesurface of the p-well 16, and is etched back within the trench 14 todefine a recessed gate 12 in a lower portion of the trench 14 for thepower MOSFET 70. The depth of the gate 12 recessed within the trench 14is within a range of about 0.2 to 0.8 microns from the opening of thetrench.

[0039] A dielectric layer 76 is deposited on the surface of the gatedielectric layer 24 and on the surface of the gate 12. The dielectriclayer 76 is for isolating the gate 12. The surface dielectric layer 76is removed, and the upper surface of the body region 16 and the uppersurface of the dielectric layer 20 within the trench 14 is planarized,as illustrated in FIG. 8.

[0040] After planarizing the upper surface of the body region 16 and theupper surface of the dielectric layer 20 within the trench 14, an n-typedopant is implanted into the body region 16 adjacent the dielectriclayer to define the source regions 26 of the power MOSFET 70. The n-typedopant, such as Arsenic or Phosphorous, is implanted using a dose withina range of about 2E15/cm² to 2E16/cm², for example, and at an energylevel within a range of about 40 to 200 keV, for example. An anneal isperformed afterwards within a temperature range of about 900 to 1,100°C.

[0041] Surface portions laterally adjacent the dielectric layer isremoved so that a portion of the dielectric layer 20 extends outwardlytherefrom, as illustrated in FIG. 9. A thickness of the surface portionsthat is removed is within a range of about 0.1 to 1 micron. As will beexplained in greater detail below, the outwardly extending dielectriclayer 20 advantageously allows self-aligned spacers to be formed.

[0042] Since the dopant concentration of the source regions 26 may bereduced when the surface layer is etched, another source implant may beperformed to enhance the doping concentration of the source regions.This enhancement may be performed using the same dose and energy levelsas previously discussed. As an alternative to the disclosed process,implantation of the n-type dopants to define the source regions 26 maybe performed after the surface portions laterally adjacent thedielectric layer has been removed to define the outwardly extendeddielectric layer 20. In this way, only one implantation is performed todefine the source regions 26.

[0043] A nitride deposition is then performed on the dielectric layer 20and on the source regions 26. The nitride deposition is etched to formspacers 80, as illustrated in FIG. 10.

[0044] Using the spacers 80 as a self-aligned mask, p-type dopants areimplanted into the body region 16 for defining source/body contactregions 82, as illustrated in FIG. 11. The p-type dopants, such asBoron, are implanted at a high energy in order to penetrate through thesource regions 26. The Boron may be implanted using a dose within arange of about 2E15/cm² to 2E16/cm², for example, and at an energy levelwithin a range of about 120 to 400 keV, for example. An anneal isperformed afterwards within a temperature range of about 900 to 1,100degrees C.

[0045] The spacers 80 are removed and a source electrode 84 is formed onthe source regions 26. The method further includes forming at least oneconductive via 86 between the source electrode 84 and the source/bodycontact regions 82. A drain electrode is on the underside of thesubstrate 8.

[0046] The source/body contact regions 82 are continuously in contactbetween the body region 16 and the source regions 26. In other words,each power MOSFET includes a source/body contact region 82. This helpsto reduce the on-resistance of the power MOSFET 70. This also helps todecrease the base resistance and the common base current gain of theparasitic BJT. The parasitic BJT will be turned on at a higher current,resulting in an improved SOA and a higher UIS capability.

[0047] In addition, the on-resistance is reduced because the cell pitchof the power MOSFET 70 is reduced as a result of the dielectric layer 20being formed completely within the trench 14. In other words, thedielectric layer 20 is not on the surface of the source regions 26 whichwould minimize the contact region between the source regions and thesource electrode 84. As a result, the body region 16, the gate 12, thesource regions 26, and the source/body contact regions 82 define a cellpitch of about 0.5 microns, for example.

[0048] Instead of using high energy to implant the dopants to define thesource/body contact regions 82, low energy may be used provided thespacers 80 are used as a self-aligned mask for removing a portion of thesource regions 26 not covered by the spacers. As best illustrated inFIG. 12, a portion of the source regions 26 not covered by the spacers80 has been removed. This power MOSFET is represented by reference 70′.

[0049] Removing a portion of the source regions 26 has the advantage ofpermitting the source/body contact regions 82 to be defined using lowenergy. The p-type dopants, such as Boron, may also be implanted using adose within a range of about 2E15/cm² to 2E16/cm², for example, but theenergy is now within a range of about 40 to 120 keV, for example. Asdiscussed above, an anneal is performed afterwards within a temperaturerange of about 900 to 1,100 degrees C. This power MOSFET is representedby reference 70′ in FIG. 12.

[0050] As another embodiment, the portion of the source regions 26 notcovered by the spacers 80 are completely removed. After the source/bodycontact regions 82 have been defined using low energy, the sourceelectrode 84 is in direct with the contact regions. This power MOSFET isrepresented by reference 70″ in FIG. 13.

[0051] An advantage of removing all of the source regions 26 not coveredby the spacers 80, and even part of the underlying body region 16, isthat the source/body contact regions 82 may be formed deeper within thebody region 16. This decreases the common base current gain of theparasitic BJT, which helps to improve device ruggedness, i.e., increasethe safe operating range (SOA) and increase the unclamped inductiveswitching (UIS) of the power MOSFET.

[0052] The depth of the source/body contact regions 82 also effects thepath of the avalanche breakdown current, as best illustrated in FIGS. 14and 15. For example, when the spacers 80 are used to etch through thesource regions 26 and into the body region 16 corresponding to a depthof 0.5 microns, for example, the simulated avalanche breakdown current90 flows to the bottom of the trench 14 before reaching the source/bodycontact regions 82, as illustrated in FIG. 14. This corresponds to ablock voltage (VDSBR) of 39.67 V.

[0053] However, by increasing the depth of the etch to 0.8 microns, forexample, the simulated avalanche breakdown current 90 has a shorter pathto follow since it does not flow to the bottom of the trench 14, asillustrated in FIG. 15. This corresponds to a block voltage (VDSBR) of36.75 V. Consequently, the trench-gated power MOSFET devices in FIG. 15are more rugged than the devices illustrated in FIG. 14.

[0054] Another aspect of the present invention is directed to the powerMOSFET 70 formed as a result of the above disclosed process. The powerMOSFET 70 comprises a semiconductor layer 8,9 having a trench 14therein, a gate dielectric layer 24 lining the trench, and a gateconducting layer 12 in a lower portion of the trench.

[0055] A dielectric layer 20 is in an upper portion of the trench 14 andextends outwardly from the semiconductor layer 8,9. Source regions 26are adjacent the outwardly extending dielectric layer 20, andsource/body contact regions 82 are laterally spaced from the gateconducting layer 12.

[0056] Another embodiment of the power MOSFET 70′ is with respect to thesource regions 26, wherein a portion of the source regions include arecess over the source/body contact regions, as best illustrated in FIG.12. In yet another embodiment of the power MOSFET 70″, the sourceregions 26 includes an opening exposing the body region 16 so that thesource electrode 84 is in contact with a source/body contact region 82,as best illustrated in FIG. 13.

[0057] Many modifications and other embodiments of the invention willcome to the mind of one skilled in the art having the benefit of theteachings presented in the foregoing descriptions and the associateddrawings. Therefore, it is to be understood that the invention is not tobe limited to the specific embodiments disclosed, and that modificationsand embodiments are intended to be included within the scope of theappended claims.

That which is claimed is:
 1. A method for making a MOSFET comprising:forming a trench in a semiconductor layer; forming a gate dielectriclayer lining the trench; forming a gate conducting layer in a lowerportion of the trench; forming a dielectric layer to fill an upperportion of the trench; removing portions of the semiconductor layerlaterally adjacent the dielectric layer so that an upper portion thereofextends outwardly from the semiconductor layer; forming spacerslaterally adjacent the outwardly extending upper portion of thedielectric layer; and using the spacers as a self-aligned mask fordefining source/body contact regions.
 2. A method according to claim 1,wherein using the spacers as a self-aligned mask comprises implantingdopants for defining the source/body contact regions.
 3. A methodaccording to claim 1, wherein using the spacers as a self-aligned maskcomprises etching the semiconductor layer not covered by the spacers. 4.A method according to claim 3, wherein the etching is performed to adepth equal to or less than about 1 micron from a surface of thesemiconductor layer.
 5. A method according to claim 1, furthercomprising forming source regions in the semiconductor layer adjacentthe outwardly extending dielectric layer before forming the spacers. 6.A method according to claim 5, further comprising forming a sourceelectrode on the source regions and on the dielectric layer.
 7. A methodaccording to claim 6, further comprising forming at least one conductivevia between the source electrode and the source/body contact regions. 8.A method according to claim 5, further comprising forming a sourceelectrode on the source regions, on the dielectric layer and on thesource/body contact regions.
 9. A method according to claim 1, furthercomprising removing the spacers.
 10. A method according to claim 1,wherein removing portions of the semiconductor layer is performed to adepth equal to or less than about 1 micron from a surface thereof.
 11. Amethod according to claim 1, wherein the gate conducting layer isrecessed in the trench within a range of about 0.2 to 0.8 microns froman opening thereof.
 12. A method according to claim 1, furthercomprising forming a body in the semiconductor layer adjacent thetrench.
 13. A method for making a MOSFET comprising: forming a trench ina semiconductor layer; forming a gate dielectric layer lining thetrench; forming a gate conducting layer in a lower portion of thetrench; forming a dielectric layer to fill an upper portion of thetrench; removing portions of the semiconductor layer laterally adjacentthe dielectric layer so that an upper portion thereof extends outwardlyfrom the semiconductor layer; forming spacers laterally adjacent theoutwardly extending upper portion of the dielectric layer; using thespacers as a self-aligned mask for etching the semiconductor layer notcovered by the spacers; and using the spacers as a self-aligned mask forimplanting dopants for defining source/body contact regions.
 14. Amethod according to claim 13, wherein the etching is performed to adepth equal to or less than about 1 micron from a surface of thesemiconductor layer.
 15. A method according to claim 13, furthercomprising forming source regions in the semiconductor layer adjacentthe outwardly extending dielectric layer before forming the spacers. 16.A method according to claim 15, further comprising forming a sourceelectrode on the source regions and on the dielectric layer.
 17. Amethod according to claim 16, further comprising forming at least oneconductive via between the source electrode and the source/body contactregions.
 18. A method according to claim 15, further comprising forminga source electrode on the source regions, on the dielectric layer and onthe source/body contact regions.
 19. A method according to claim 13,further comprising removing the spacers.
 20. A method according to claim13, wherein removing portions of the semiconductor layer is performed toa depth equal to or less than about 1 micron from a surface thereof. 21.A method according to claim 13, wherein the gate conducting layer isrecessed in the trench within a range of about 0.2 to 0.8 microns froman opening thereof.
 22. A method according to claim 13, furthercomprising forming a body region in the semiconductor layer adjacent thetrench.
 23. A MOSFET comprising: a semiconductor layer having a trenchtherein; a gate dielectric layer lining the trench; a gate conductinglayer in a lower portion of the trench; a dielectric layer in an upperportion of the trench and extending outwardly from said semiconductorlayer; source regions adjacent the outwardly extending dielectric layer;and source/body contact regions laterally spaced from said gateconducting layer.
 24. A MOSFET according to claim 23, further furthercomprising a source electrode on said source regions and on saiddielectric layer.
 25. A MOSFET according to claim 24, further comprisingat least one conductive via between said source electrode and saidsource/body contact regions.
 26. A MOSFET according to claim 23, whereina portion of said source regions include a recess over said source/bodycontact regions.
 27. A MOSFET according to claim 23, wherein a portionof said source regions include an opening exposing said source/bodycontact regions; and further comprising a source electrode on saidsource regions, on said dielectric layer, and on said source/bodycontact regions.
 28. A MOSFET according to claim 23, wherein saidoutwardly extending dielectric layer extends from said source regionsequal to or less than about 1 micron.
 29. A MOSFET according to claim23, wherein the gate is recessed in the trench within a range of about0.2 to 0.8 microns from an opening thereof.
 30. A MOSFET according toclaim 23, wherein said source/body contact regions are recessed withinsaid semiconductor layer adjacent said source regions.
 31. A MOSFETaccording to claim 30, wherein an upper surface of the recess is equalto or less than a depth of about 1 micron from a surface of thesemiconductor layer.